1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device which stores data by accumulating charges in a floating gate of each memory cell. More particularly, the present invention relates to an improved technique for driving word lines of such a non-volatile semiconductor storage device using a hierarchical word line drive circuit.
2. Description of Related Art
Control gates are generally used as word lines in non-volatile semiconductor storage devices such as flash memories and EEPROMs (electrically erasable programmable read-only memories) which are configured to store data by accumulating charges in a floating gate of each memory cell. By applying an appropriate voltage to a word line (i.e., control gate), it is possible to program, erase, or read desired data to/from each memory cell.
Recent non-volatile semiconductor storage devices are configured such that both positive and negative potentials can be applied to word lines as disclosed in Japanese Patent Laid-Open No. 2005-317138. Such a configuration makes it possible to downsize gates of transistors which compose memory cells and word line drive circuits, and thereby downsize the non-volatile semiconductor storage devices.
Another trend in recent non-volatile semiconductor storage devices is hierarchical design of word line drive circuits. The recent non-volatile semiconductor storage devices use hierarchical word line drive circuits to make it possible to drive a large number of word lines. For example, Japanese Patent Laid-Open No. 10-3794 discloses a hierarchical word line drive circuit consisting of block decoders, gate decoders, and sub-decoders.
One of requirements for a hierarchical word line drive circuit is that the drivers in the final word line drive stage have a simple configuration. There are as many drivers in the final stage as there are word lines, and thus simplification of driver configuration in the final stage is very useful in downsizing the word line drive circuit.
Japanese Patent Laid-Open No. 2001-43693 discloses a hierarchical word line drive circuit in which drivers in the final word line drive stage consists of two MOS transistors. FIG. 1 is a circuit diagram showing a configuration of the word line drive circuit disclosed in the patent document. The word line drive circuit shown in FIG. 1 has an even-numbered global decoder 100, odd-numbered global decoder 120, row local decoder 140, row partial decoder 160, and block decoder 180.
The even-numbered global decoder 100 has a NAND gate 102, NOR gate 104, and level shifter 106 and drives an even-numbered global word line EGWLi. The odd-numbered global decoder 120 has a NAND gate 122, NOR gate 124, and level shifter 126 and drives an odd-numbered global word line OGWLi.
The row local decoder 140 is a circuit which drives local word lines WLi connected to memory cells (not shown). The row local decoder 140 consists of PMOS transistors P10 to P24 and NMOS transistors N10 to N24. The row partial decoder 160 has a NAND gate 162 and level shifter 164 and generates word line selection signals PWL0 to PWL7. The block decoder 180 has a NAND gate 182, AND gate 184, and level shifter 186 and supplies the row local decoder 140 with a negative voltage used for erasing operations.
With the word line drive circuit in FIG. 1, each local word line is driven by a driver consisting of two MOS transistors (one PMOS transistor and one NMOS transistor). For example, the local word line WL0 is driven by a driver consisting of the PMOS transistor P10 and NMOS transistor N10 while the local word line WL1 is driven by a driver consisting of the PMOS transistor P11 and NMOS transistor N11.
The word line drive circuit in FIG. 1 operates as follows in write operations. An operation performed when the local word line WL2 is selected will be described below. When the write operations are performed, the even-numbered global decoder 100 drives the even-numbered global word line EGWLi at 0 V. Consequently, the PMOS transistors P10 to P16 turn on and the NMOS transistors N10 to N16 turn off. On the other hand, the odd-numbered global decoder 120 drives the odd-numbered global word line OGWLi at 10 V. Consequently, the PMOS transistors P10 to P16 turn off and the NMOS transistors N10 to N16 turn on. The row partial decoder 160 sets the word line selection signal PWL2 at 10 V and sets the remaining word line selection signals PWL0, PWL1, and PWL3 to PWL7 at ground potential. The block decoder 180 generates a 0 V potential.
Consequently, the local word line WL2 is electrically connected to the word line selection signal PWL2 with a potential of 10 V via the PMOS transistor P12, and is driven at 10 V.
In read operations, the word line drive circuit in FIG. 1 operates in the same manner as in write operations except that a voltage of 5 V is used instead of 10 V.
A feature of the word line drive circuit in FIG. 1 is that each local word line is driven by only two MOS transistors. This simple configuration is effective in reducing overall size of the word line drive circuit.
[Patent Document 1] Japanese Patent Laid-Open No. 2005-317138
[Patent Document 2] Japanese Patent Laid-Open No. 10-3794
[Patent Document 3] Japanese Patent Laid-Open No. 2001-43693
However, the word line drive circuit in FIG. 1 has a problem in that part of unselected local word lines is brought into a floating state. The local word lines WL1, WL3, WL5, and WL7, which are electrically connected to outputs of the block decoder 180 via the NMOS transistors N18, N20, N22, and N24, respectively, are driven at 0 V to be sure, but the local word lines WL0, WL4, and WL6 are brought into a floating state. Gate and source potentials of the PMOS transistors P10, P14, and P16 are all 0 V. Thus, the PMOS transistors P10, P14, and P16 do not turn on. Neither do the NMOS transistors N10, N14, and N16, as described above. Consequently, the local word lines WL0, WL4, and WL6 are cut off from outputs of both row partial decoder 160 and block decoder 180 and brought into a floating state.
In this regard, Japanese Patent Laid-Open No. 2001-43693 states that since the local word lines WL1, WL3, WL5, and WL7, which are electrically connected to outputs of the block decoder 180 via the NMOS transistors N18, N20, N22, and N24, respectively, are driven at 0 V, the local word lines WL0, WL4, and WL6 are electrically shielded, which prevents coupling among word lines.
However, it is not desirable from the viewpoint of stability of operation that local word lines, which are long and thick, enter a floating state. When local word lines enter a floating state, data may be read or written erroneously due to noise. Desirably, unselected local word lines are kept at a fixed potential (typically at ground potential).